In memories there is an address comprised of binary signals which specify a particular location in that memory. The address is generally divided into a row address and a column address. The row address selects a word line which is enabled. The column address selects one or more bit lines which are then used for providing data. In the case of static random access memories (SRAMs), each memory cell is coupled to a pair of bit lines so that each pair is decoded together. As memories become larger, the number of transistors required to perform a row or column decode becomes larger. For example, in the case of a 64K.times.1 memory, there are 16 address signals required to specify a particular location. This could be arranged as 8 column address signals and 8 row address signals. To use standard logic-gate type decoding would require 8 N channel transistors and 8 P channel transistors at each bit line location that is to be decoded.
To avoid this, predecoding techniques have been developed to avoid having such a large number of transistors at each bit line or word line. One of the objects then of any predecoding technique is to reduce the number of transistors at the particular bit line or word line location. In CMOS, two binary signals can be decoded using four transistors, two N channel transistors and two P channel transistors. This can be reduced to three transistors if both the true and complement of one of the two binary signals are available. This technique has been used to reduce the number of transistors at the bit line decode location. The requirement of both true and complements, however, is a disadvantage. Supplying the true and complement requires additional space on the chip for the conductors which carry these extra signals.